Power Consumption of the Shared L2 Cache Dynamic Partition in CMP
نویسندگان
چکیده
With the trend towards Chip Multi-processors(CMP),the size of Cache increases apparently. But these caches propose larger and larger proportion in the total power consumption. This paper proposes a new mechanism that implemented in CMP to reduce energy consumption, which based on dynamically way-adaptable cache. The mechanism mainly consists of way reallocate module and dynamic power control module. Way reallocate module reassign ways between cores based on thread’s working set on the execution of the program. Our mechanism implements low power consumption by dynamic power control module. The proposed scheme based on dynamically wayadaptable cache is implemented and simulated. We applied several programs selected from SPEC2006 as benchmarks. Experiment results show our present scheme can reduce 11.9% power consumption on average on the CMP that contains 4 cores, (12.38 % on average in 8core CMP) with no performance degrade.
منابع مشابه
Dynamic Power Partitioning and Control for Performance Optimization in Chip Multiprocessors
Since power consumption has become a major constraint for the further throughput improvement of chip multiprocessors (CMPs), a key challenge is to optimize the performance of a CMP within a power budget limited by the CMP’s cooling, packaging, and power supply capacities. Most existing solutions rely solely on dynamic voltage and frequency scaling (DVFS) to adapt the power consumption of CPU co...
متن کاملCMP L2 NUCA Cache Power Consumption Reduction Technique
We analyze how applications use banks in a large shared CMP L2 D-NUCA cache depending on their locality and we define a power consumption model. Then we develop a mechanism to dynamically turn on and off a bankcluster in order to reduce the energy consumption. 1. CMP Way Adaptable Our system is a large shared L2 D-NUCA cache in CMP environment (Figure 1). In this architecture each bank is acces...
متن کاملTechniques for reducing power consumption in CMP NUCA caches
Current trend of technology scaling makes it possible to put a huge number of transistors on a single die. While dynamic power consumption can benefit from technology scaling, static power consumption get worse, thus making the latter the dominant factor of power consumption in future microprocessor systems. As on-chip cache memories require the most part of chip area and number of transistors,...
متن کاملTechniques for reducing power consumption in CMP Nuca cache
Current trend of technology scaling makes it possible to put a huge number of transistors on a single die. While dynamic power consumption can benefit from technology scaling, static power consumption get worse, thus making the latter the dominant factor of power consumption in future microprocessors system. As on-chip cache memories require the most part of chip area and number of transistors,...
متن کاملOn-Chip Power Minimization Using Serialization-Widening with Frequent Value Encoding
In chip-multiprocessors (CMP) architecture, the L2 cache is shared by the L1 cache of each processor core, resulting in a high volume of diverse data transfer through the L1-L2 cache bus. High-performance CMP and SoC systems have a significant amount of data transfer between the on-chip L2 cache and the L3 cache of off-chip memory through the power expensive off-chip memory bus. This paper addr...
متن کامل